***(submitted)
J.-Y. Park, S.-H. Kim, *J.-W. Nam, "Analysis of ROM-based DDFS Architecture Employing Quarter Method", International Conference on Electronics, Information, and Communication (ICEIC) 2023, Singapore, Feb. 2023.
J.-W. Hyun, *J.-W. Nam, "Regression Model-based VCO Design Optimization Technique", International Conference on Electronics, Information, and Communication (ICEIC) 2023, Singapore, Feb. 2023.
D. Kim, *J.-W. Nam, J.-P. Hong, "Analysis of Silicon Photodiodes", International Conference on Electronics, Information, and Communication (ICEIC) 2023, Singapore, Feb. 2023.
H.-J. Lee, H.-C. Lee, J. Yoo, Y.-K. Cho, *J.-W. Nam, "Analysis on Efficiency of DC-DC Converter through Power-Loss Modeling & Measurement", the 5th ISE Conf., Seoul, Dec. 2022.
H. Yoo, J.-W. Hyun, *J.-W. Nam, "인공신경망을 이용한 부트스트랩 S/H 설계 최적화", the 5th ISE Conf., Seoul, Dec. 2022.
J.-W. Hyun, J.-Y. Kim, S.-J. Kim, *J.-W. Nam, "Study on Jitter Analysis and Reduction Methods in DLL", Fall annual conference of IEIE, Gonjiam, Nov. 2022.
H.-C. Lee, H.-J. Lee, J. Yoo, *J.-W. Nam, “Loss analysis and modeling of asynchronous buck-converter”, Summer annual conference of IEIE, Jeju, Jun. 2022.
D. Kim, H. Yoo, *J.-W. Nam, “Implementation of low-cost linear CMOS temperature sensor for biomedical application”, Summer annual conference of IEIE, Jeju, Jun. 2022.
J. Yoo, J.-W. Nam, J.-P. Hong, “Study on discard-rate of SRAM-based PUF”, Summer annual conference of IEIE, Jeju, Jun. 2022.
S. Park, J.-W. Nam, and S. K. Gupta, “HW-BCP: A custom hardware accelerator for SAT suitable for single chip implementation for large benchmarks,” the 26th Asia and South Pacific Design Automation Conf., Jan. 2021.
J.-W. Nam and Y. K. Lee, "Machine-learning based analog and mixed-signal circuit design and optimization," the 35th International Conf. on Information and networking (ICOIN), Jan. 2021.
H. W. Kwon, J.-W. Nam, and Y. K. Lee, “Generative adversarial attacks on fingerprint recognition systems,” the 35th International Conf. on Information and networking (ICOIN), Jan. 2021.
J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS,” IEEE Custom Integrated Circuits Conf., Apr, 2019, (Best Student Paper Award).
J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “Low-power High Dynamic-range ADC with over GHz Bandwidth using Cost-efficient Multi-bit/cycle SAR ADC,” GOMATech 2018.
J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2016, pp.154–156.
J.-W. Nam, D. Chiong, and S.-W. M. Chen, “A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65 nm CMOS,” IEEE Custom Integrated Circuits Conf., Sep. 2013, pp. 1–4.
J.-W. Nam, Y.-D. Jeon, S.-J. Yun, T. M. Roh, and J.-K. Kwon, “A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS,” in Proc. IEEE ISOCC, 2011, pp. 405–407.
J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, S.-G. Lee, and J.-K. Kwon, “A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS,” in Proc. IEEE ESSCIRC, 2009, pp. 468–471.
D. Kang, H. Lim, J.-W. Nam, M. S.-W. Chen, J. Yoon, “VCSEL-Based Stretchable Blood Flow Sensors”, A meeting of the materials Research Society, Boston, U.S., Nov. 2017.
Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, W.-Y. Lee, K.-T. Hong, and J.-K. Kwon, “A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS,” IEEE Custom Integrated Circuits Conf., Sep. 2010, pp. 1–4.
H.-B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “A CMOS sigma-delta modulator for a digital electret microphone with a high input-impedance preamplifier,” 15th Korean Conference on Semiconductors, Phyeong-Chang, Feb. 2008.

Journal Publications

[2023]

J.-W. Hyun and J.-W. Nam, "AMS Circuit Design Optimization Technique Based on ANN Regression Model with VAE Structure", IEEE ACESS, June 2023. (accepted)
J. Kim, J. H. Han, J.-W. Nam, K. H. Cho, "CMOS Interconnect Electronics Architecture for Reliable and Scalable Quantum Computer", J.inst.Korean.electr.electron.eng.Vol.27,No.1,12~18,March 2023.

[2022]

J.-W. Nam, J. Kim, and J.-P. Hong, "Stochastic Cell- and Bit-Discard Technique to Improve Randomness of a TRNG," MDPI Electronics, vol. 11, no. 11, June 2022. (SCIE, IF=2.397)
J.-W. Nam, J.-H. Ahn, and J.-P. Hong, "Compact SRAM-based PUF Chip Employing Body Voltage Control Technique," IEEE ACCESS, vol. 10, pp. 22311-22319, Feb. 2022. (DOI: 10.1109/ACCESS.2022.3153359, SCIE, IF=3.367)
J.-W. Nam, Y.-K. Cho and Y. K. Lee, "Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition," MDPI Electronics, vol. 11, no. 3, Jan. 2022. (SCIE, IF=2.397)

[2021]

Y.-K. Cho, J.-W. Nam, S.-W. Lee, "A Low-Power Class-C Voltage-Controlled Oscillator with Robust Start-Up and Compact High-Q Capacitor Array," IEEE Trans. Circuits Syst. II, Exp. Briefs, Oct. 2021. (DOI: 10.1109/TCSII.2021.3116978, SCIE, IF=3.292)
Y.-K. Cho, J.-W. Nam, "Three-Dimensional Selective Oxidation Fin Channel MOSFET Based on Bulk Silicon Wafer," Journal of Convergence for Information Technology, vol. 11, no. 11, pp. 159-165, Nov. 2021. (KCI)
J.-W. Nam, Y.-K. Cho, "5-bit FLASH A/D Converter Employing Time-interpolation Technique," Journal of Convergence for Information Technology, vol. 11, no. 9, pp. 124-129, Sept. 2021. (KCI)

[~ 2020]

J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer,” IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 557 - 567, Mar. 2020.
J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1765-1779, Jun. 2018
J.-W. Nam, and S.-W. M. Chen, “An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 10, pp. 1628 - 1638, Oct. 2016.
J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “A 12-Bit 200-MS/s pipelined A/D converter with sampling skew reduction technique,” Elsevier Microelectronics Journal, no. 11, vol. 42, pp. 1225-1230, Nov. 2011.
Y.-D. Jeon, J.-W. Nam, K.-D. Kim, T. M. Roh, and J.-K. Kwon, “A dual-channel pipelined ADC with sub-ADC based on flash–SAR architecture,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 11, pp. 741–745, Nov. 2012.
H. B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “Single-chip A/D converter for digital microphones with on-chip preamplifier and time-domain noise isolation,” Electronics Letter, vol. 45, no. 3, pp. 151-153, 2009.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 9-bit 80 MS/s successive approximation register analog-to-digital Converter with a capacitor reduction technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, pp. 502–506, Jul. 2012.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications,” Elsevier Microelectronics Journal, vol. 42, no. 12, pp. 1335–1342, Jul. 2011.
Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, S. -C, Lee, and J.-K. Kwon, “A 1.2 V 12 b 60 MS/s CMOS analog front-end for image signal processing applications,” Elsevier ETRI Journal, vol. 31, no. 6, Dec. 2009.

Conference Publications

- Ecclesiastes III-I -

“To every thing there is a season, and a time to every purpose under the heaven:”

PUBLICATIONS

Abstract

S.-Y. Lim, C.-W. Kim, *J.-W. Nam, “High-Speed PRBS Generator for PAM-4 Transmitter,” the 21th RF/Analog workshop, 2021.

Pre-publication

S. M. Kim, Y. H. Jeong, and J.-W. Nam, “Optimizing EV Chargers Location via Integer Programming,” Systems and Control (eess.SY), 17. Mar. 2023.

Granted Patents

J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “Algorithmic analog-to-digital converter,” US 7847713 B2.
J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “Pipeline analog-to-digital converter,” US 8164497 B2.
S.-C. Lee, J.-W. Nam, Y.-D. Jeon, J.-K. Kwon, “Method of algorithmic analog-to-digital conversion and algorithmic analog-to-digital converter,” US 7705764 B2.
M. H. Cho, Y. G. Kim, J.-W. Nam, and J.-K. Kwon, “Read-out circuit with high input impedance,” US 8300850 B2.
Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, J.-K. Kwon, “Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same,” US 7999719 B2.
Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, J.-K. Kwon, “Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same,” US 7978117 B2.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “High-speed multi-stage voltage comparator,” US 7977979 B2.
Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, J.-K. Kwon, “Reference voltage supply circuit including a glitch remover,” US 8547081 B2.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Successive approximation register analog-digital converter and method for operating the same,” US 8164504 B2.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Successive approximation register analog-digital converter and method of driving the same,” US 7893860 B2.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Digital-to-analog converter,” US 8059022 B2.
Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Offset-voltage calibration circuit,” US 8264268 B2.